GRAPH-AWARE MULTI-TASK LEARNING FOR EARLY PREDICTION OF TIMING VIOLATIONS AND ROUTING CONGESTION IN DIGITAL IC PHYSICAL DESIGN
Keywords:
Physical design, Routing congestion, Static timing analysis, Graph neural networks, Multi-task learning, Machine learning for EDAAbstract
Routing congestion and timing closure are the two dominant, and physically coupled, bottlenecks of digital integrated-circuit physical design, yet machine-learning predictors have almost always targeted them in isolation. We present GAMT-Net, a graph-aware multi-task network that jointly predicts per-cell routing congestion and per-cell timing slack from a single netlist-and-placement graph at the pre-routing stage. Its core novelty is a congestion-conditioned timing (CcT) module that feeds the timing head with the predicted congestion embedding of each cell together with the mean congestion embedding of its fan-in-cone predecessors, explicitly encoding the congestion-detour-delay causality that links the two tasks; task losses are balanced by homoscedastic uncertainty weighting. Because large public layout datasets are access-gated, we construct a fully reproducible, physically-grounded benchmark of 220 synthetic designs (166,822 cells) whose labels are produced by a rectangular-uniform-wire-density congestion estimator and a longest-path static-timing engine with congestion-dependent interconnect delay. On held-out designs, multi-task learning improves slack correlation over single-task learning (0.510 vs. 0.482), and the CcT module delivers the largest single gain, raising slack Pearson correlation to 0.543 and violation-classification AUC to 0.806, while congestion prediction reaches r = 0.86 and hotspot AUC 0.89. Ablations show that graph structure is essential, that a naive graph-convolutional encoder over-smooths the directional timing signal, and that netlist connectivity rather than spatial proximity drives timing. All code and data are released for reproducibility.References
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